Autonomous Instruction Memory Equipped with Dynamic Branch Handling Capability

portable information appliances, the extraordinary power consumption ratio of memory accesses promotes importance of efficient memory system design to an ultimate. We address the following issues: how to minimize memory bandwidth requirement for instruction accesses, and how to minimize memory access delay, again for instruction accesses. Then we propose to move dynamic branch handler (e.g., branch target buffer) from CPU to the instruction memory side (i.e., bind BTB and instruction memory in the same bus module). We present such a design which can help us achieve the following goals: 1. To greatly reduce instruction address bus traffic, which saves much bus power; 2. To autonomously pipe instructions to the CPU, without having to wait for the addresses from CPU, which saves much delay. Using programs in MediaBench as test programs, our design shows that the instruction address bus traffic reduction is 83%, even by accounting for repeated and redundant target address traffic in instruction decode stage. Furthermore, we suggest using very simple techniques to eliminate transmission of most of these target addresses.